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Ordering number : EN4793A
Thick-Film Hybrid IC
STK301-220
7-band, 2-channel Electronic Graphic Equalizer
Overview
The STK301-220 is a hybrid IC (HIC) for electronically controlled graphic equalizer applications and is equipped with on-chip electronic volume control for 7-band, 2channel graphic equalization, thereby permitting onetouch up-down control of all band gains. The STK301220 is a hybrid IC which combines SC system and photoresist techniques with folded board construction while incorporating Sanyo's unique insulated metal substrate technology (IMST) to the base.
Applications
* Car stereos * Portable radio-cassette players * Home stereos
-- One-touch up-down control of all band gains. -- Immediate recall of preferred frequency levels tailored to suit musical selections. This is possible using preset functions to retrieving items from one-touch memory. -- Such functions as setting all bands to 0 dB (flat function), or switching frequency characteristics from 0 dB to center (reverse function) may be simply performed with supported software. -- Dual control lines permit mutual use with display LSI and help to simplify wiring between microcontroller and LSI. * Minimal operating shock noise when boost or cut is used.
Package Dimensions
unit : mm 4143
[STK301-220]
Features
* All bands are set for L/R simultaneous 2 dB incremental operation (typ). * All bands are equipped with 13 positions and range between +12 dB maximum boost to -12 dB maximum cut. * Crossover frequencies include fo; 60 Hz, 150 Hz, 400 Hz, 1 kHz, 2.5 kHz, 6 kHz and 15 kHz. * The following features can be made available with an electronic graphic equalizer system which incorporates the 3-IC construction consisting of the STK301-220, a controller (universal microcontroller) along with the display LSI (LC75821LCD, LC7565FLT, LED):
Specifications
Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Symbol VDD-VEE max Maximum supply voltage VCC1 max VCC2 max Input voltage Allowable power dissipation Operating temperature Storage temperature VI1 VI2 Pd max Topr Tstg CLK, DI, IN1, IN2 CLK, DI, IN1, IN2 Conditions Ratings 16 18 (36) 7 0 to VCC2 + 0.3 VEE - 0.3 to VDD + 0.3 920 -20 to +70 -40 to +100 Unit V V V V V mW C C
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N3096HA (OT)/82294TH (OT) 5-3398 No. 4793-1/8
STK301-220 Recommended Operational Voltage at Ta = 25C
Parameter Symbol VDD/VEE Supply voltage VCC1 VCC2 VSS = 0 V VSS = 0 V VSS = 0 V Conditions Ratings 7 (14) 7 (14) 5 Unit V V V
Allowable Operating Ranges at Ta = 25C, VSS = 0 V
Parameter Symbol VDD-VEE Supply voltage VCC1 VCC2 Input high level voltage Input low level voltage Input pulse width Setup time Hold time Operating frequency VIH VIL tOW tsetup thold fopg CLK, DI CLK, DI CLK DI DI CLK Conditions Ratings 7.5 to 15.0 4 to 18 (8 to 36) 4.5 to 5.5 0.8 VCC2 to VCC2 0.2 VCC2 from 1 from 1 from 1 up to 330 Unit V V V V V s s s kHz
Operating Characteristics at Ta = 25C, VSS = 0 V, VDD/VEE = 7 V, VCC1 = 7 V, VCC2 = 5 V, f = 1 kHz All bands flat, using the specified test circuit
Ratings Parameter Symbol IDD Current dissipation ICC1 ICC2 Voltage gain Total harmonic distortion Crosstalk Output noise voltage Setting error VG THD C.T. VNO B f (1) f (2) f (3) Frequency response f (4) f (5) f (6) f (7) f = 60 Hz f = 150 Hz f = 400 Hz f = 1 kHz When operating at f = 1 kHz, all bands are flat and f = 2.5 kHz VO = -10 dB set at 0 dB. VIN = -10 dB-4.0 f = 1 kHz, VO = 1V, 30 kHz L.P.F f = 20 kHz, VIN = 0 dB Rg = 0 , 10 Hz to 30 kHz B.P.F -1 10 10 10 10 10 10 10 12 12 12 12 12 12 12 45 -1.0 +2.0 0.005 55 9 25 +1 14 14 14 14 14 14 14 VDD/VEE = 7 V, VCC1 = 7 V,VSS = 0 V VCC2 = 5 V 20 Conditions min typ max 1 30 1 dB 0.1 % dB V dB dB dB dB dB dB dB dB Unit mA mA mA
f = 6 kHz f = 15 kHz
Note: With constant voltage power supply. The supply voltage figures in parentheses indicate the voltages when a single voltage power supply is used.
Internal Equivalent Circuit
No. 4793-2/8
STK301-220 Sample Application Circuit Single Power Supply
Unit (resistance: , capacitance:F)
Split Power Supply
Unit (resistance: , capacitance:F)
No. 4793-3/8
STK301-220 Pin Descriptions
Pin No. 1 2, 21 3 4 5 6 7 8 9 10 11 12 13 14 Pin name +VCC1 DC OUTPUT 1 NF 1 1IN 1 INPUT 1 1IN 2 VSS VEE CLK DI +VCC2 GND (-VCC1) VDD Functions Power supply pin used for + power supply to IC2 and IC3 graphic equalizer. Pin for 1/2 VCC1 decoupling capacitor of graphic equalizer IC. When shortened, power supply becomes more effective and ripples are vulnerable. Output pin 1. Inverting input for the graphic equalizer IC2 internal operational amplifier. Audio signal input 1 (INPUT1) for electronic volume control IC1 Input impedance for input pin 1 rated at approximately 60 k (1 kHz, flat). Audio signal input 2 (INPUT1) for electronic volume control IC1 Power supply pin connected to ground (GND). Power supply pin used for audio signal power supply to electronic volume control section. When single power supply is used, connect to VSS. Input pin for data from CPU according to Schmitt inverter format. Input pin for clock from the CPU according to Schmitt inverter format. Power supply pin rated at +5 V (typ). Make sure that VCC2 does not onset before VDD. Power supply pin for ground (- power supply) of IC2 and IC3 graphic equalizer. Power supply pin used for audio signal power supply to electronic volume control section. Select pin for applications using two ICs. Input "1" to initiate key code 7C3 for connecting to VDD. Input "0" to initiate key code 7C2 for connecting to VEE. Audio signal input 2 (INPUT2) for electronic volume control IC1 Input impedance for input pin 2 rated at approximately 60 k (1 kHz, flat). Audio signal input 1 (INPUT2) for electronic volume control IC1 Inverting input for the graphic equalizer IC3 internal operational amplifier. Output pin 2.
15
S
16 17 18 19 20
2IN 2 INPUT 2 2IN 1 NF 2 OUTPUT 2
Note: Refer to LC7522 or LC7523 specifications concerning pins which do not appear here and are hybrid IC (HIC) pins connected directly to a LC7522 or LC7523 pins.
Description of Operation The STK301-220 is a hybrid IC (HIC) with a 7-component 2-channel construction for electronically controlled graphic equalizer applications. It employs an LC7522 for graphic equalizer electronic volume control and an M5229 for 7component graphic equalizer functions.
Figure 1 Equivalent Circuit Block Diagram
No. 4793-4/8
STK301-220 Pins f (1) through f (7) are used as pin connections for the LC7522 band filter. Supported frequencies and their pin assignments are listed in the following. Pin Name f (1) f (2) f (3) f (4) f (5) f (6) f (7) Frequency 60Hz 150Hz 400Hz 1kHz 2.5kHz 6kHz 15kHz
In order to minimize the noise which occurs during changeover, connections are made using 1 M resistors from pins f (1) through f (7) to 1/2 VCC1.
Resistor Equivalent Circuit (single band) Principles of Operation The graphic equalizer section is constructed from 7 resonance circuits and output buffer amplifiers (every channel); variable resistors (LC7522) and resonance circuit capacitors C1 and C2 are built-in. Resonance circuits utilize semiconductor inductors and apply resonation to reduced impedance; all frequency gains are altered. 1. Resonance Circuit Semiconductor inductors replace the L of the R, L, C series resonance circuit with a CR element passing through the buffer function of active elements such as the transistor and op-amp (operational amplifier), thereby effecting the equivalent operation of a R, L, C series resonance circuit. The STK301-220 resonance circuit buffer is constructed using transistors and arranged as illustrated in Figure 2. Resonance frequency fo is determined using the following formula: fo = 2 1 C1 * C2 * R1 * R2 Figure 2 Resonance Circuit 2. Flat, Boost and Cut Gains matching resonance circuit frequency gains are altered by altering the built-in resonance circuits and electronic volume control. Figure 3 is presented to describe the equivalent circuit. Z represents the impedance of the resonance circuit in Figure 2.
Figure 3 Equivalent Circuit
No. 4793-5/8
STK301-220 3. Flat When the volume control is set to the midrange position and Ri=RNF, the following relationships are established: R/2 ei' = * ei Ri = R/2 AV = RNF + R/2 R/2 in which
eo = AV*ei' = ei with no relation to the resonance circuit and frequency characteristics become flat. When VR is set to R, the resistance value using the VR center position becomes R/2. 4. Boost When the volume control is set to the boost position, the resonance circuit is linked to the NF loop of the output buffer amplifier. Under these circumstances and when RRi and RNF, the following relationship exist: AV = RNF + Z Z
is established and output voltage eo is calculated as eo = AV*ei = RNF + Z * ei Z
The gain becomes a minimum when the resonance circuit has Z at a minimum so that the frequency option is boosted. 5. Cut When volume is set to the cut side, resonance circuit is linked to the input side of the output buffer amplifier. Under these circumstances and when ignoring R similarly to boost, the following relationship exist: Z ei' = * ei, AV = 1 Ri+Z is established and output voltage eo is calculated as eo = AV*ei' = Z * ei Ri+Z
The gain becomes a minimum when the resonance circuit has Z at a minimum so that the frequency option is cut. 6. Resonance Circuit Crest Acuteness (Q) Resonance circuit crest acuteness is determined by comparing frequency widths 2 - 1 for GV max/2 where GV max represents point 0 as the maximum value of the resonance circuit crest. The following formula is used to calculate the value for Q: Q = C1 * R2 C2 * R1 As the value for Q becomes larger, the participating frequency bandwidth of the resonance circuit becomes narrower. Although neighboring bands distinction is precise, the swell of frequency characteristics under total boost is larger while the peak of the resultant frequency is lowered.
No. 4793-6/8
STK301-220 With the STK301-220, few crossover bands exist with an increase in swell during total boost. Pass-band-ripple (P.B.R.) width at this time is 4 dB with Q set at 3.5 fore and aft.
Data Code 1. Turning on the power initiates a process which transmits no data (0) for 60 clock cycles (initialization clock). When data is stopped en route, the remaining data is sent only after the clock has been initialized. 2. Using DI and CLK in conjunction with LC75821 (or equivalent) involves the transmission of the maximum initialization clock to those devices involved.
Things to Note 1. A 1000pF rated capacitor (or higher) should be installed between the current pin and VSS. 2. When the control signal on the microcontroller side onsets faster than STK301-220's VDD, a resistor rated at 2 k or more should be placed on the DI and CLK line. 3. Since the STK301-220 is equipped with a built-in CMOS LSI, sufficient caution should be extended to damage caused by static electricity. 4. Refer to the specification sheet for itemized details about the LC7522.
No. 4793-7/8
STK301-220
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of August, 1997. Specifications and information herein are subject to change without notice. No. 4793-8/8

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